1. Field of the Invention
The present invention relates to a RISC (Reduced Instruction Set Computer) type microprocessor.
2. Description of the Related Art
A RISC processor has a set of instructions that allows the number of calculations to become minimum. A pipeline process of the RISC processor allows all instructions to be executed in the same and short time period. The bit length of instructions of a 32-bit RISC processor is fixed to 32 bits. Thus, in the RISC processor, the bit length of instructions is fixed and the instructions are simplified. With inter-register operations, most instructions can be executed in one clock cycle and thereby the pipeline process can be easily performed.
In the conventional 32-bit RISC processor, the bit length of instructions is fixed to 32 bits. However, the code efficiency of instructions of 32-bit fixed length is not high. In a RISC processor having variable length instructions, the load applied to the decoding portion becomes large. In addition, it takes a long time to perform a pipeline process for variable length instructions. To solve this problem, a branch cache is required. Thus, the circuit scale becomes large. To solve such a problem, the applicant of the present invention has proposed a RISC processor having 16-bit fixed instructions for improving code efficiency.
A 32-bit RISC processor has an address space of 4 Gigabytes (Gbytes). In the RISC processor, when a logical address is converted into a physical address, for mapping the address to a space of 4 Gbytes, a 1p.x macro instruction is provided. Conventionally, the 1p.x macro instruction is performed by dividing an LPI instruction into four instructions. Thus, a long type (32 bit) register branch instruction requires five instructions for 10 bytes.
In other words, conventionally, an LPI (Load Position Immediate) instruction as shown in FIGS. 17A and 17B is used. The LPI instruction is composed of 16 bits as shown in FIG. 17A. In the instruction LPI, the high order six bits represent an operation code. The next two-bits BP represent the position of the bit pattern as shown in FIG. 17B. When the value of BP is "11", it represents the highest position (HH). When the value of BP is "10", it represents the next highest position (HL). When the value of BP is "01", it represents the third highest position (LH). When the value of BP is "00", it represents the lowest position (LL). As shown in FIG. 17A, the next eight bits represent an operand designated by the value of an immediate. Thus, in the long type register branch instruction, the instruction LPI is divided into four instructions each of which is composed of eight bits. Thus, at least five instructions are required as a long type register branch instruction.